Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog
简介：
本书解释了如何编写Verilog来描述寄存器传输级别 (RTL) 的芯片设计，以与验证过程合作的方式，基于实际的大规模产品设计过程和工具经验。
英文简介：
This book explains how you can write Verilog to describe chip designs at the Register-Transfer Level (RTL) in a manner that cooperates with verification processes, based on the reality that comes from actual large-scale product design process and tool experience.
- 书名
- Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog
- 译名
- 可验证 RTL 设计原则：支持 Verilog 验证过程的功能编码风格
- 语言
- 英语
- 年份
- 2002
- 页数
- 272页
- 大小
- 2.02 MB
- 下载
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog.pdf- 密码
- 65536
最后更新：2025-04-12 23:57:34